1. Field of the Invention
The present invention relates to field-effect transistors, and more particularly, to structures for power field-effect transistors.
The metal-oxide-semiconductor field-effect transistor (MOSFET) generally has a gate electrode or bus which is separated from a semiconductor material by an insulating layer. The gate electrode, which is often made of polysilicon, is disposed over a channel in the semiconductor material defined by the drain, gate and source regions of the device. A second insulating layer is deposited on the gate electrode, and a metal such as aluminum is evaporated over the second insulating layer to form a source electrode metallization layer. In order to provide contact to the source regions of the semiconductor material, openings are provided in the gate electrode and insulating layers so that a portion of the metal is also deposited at various locations on the source regions.
A single power MOSFET generally has a single large drain region formed by the semiconductor substrate and an epitaxial layer on the substrate. Within the semiconductor epitaxial layer are a large number of gate regions, with a source region located within each gate region. The gate electrode also often has a plurality of individual areas, each of which is disposed over the semiconductor between adjacent source regions. Each gate electrode area is often referred to as a gate bus. The metallization layer contacts each source region thereby interconnecting the source regions. The gate busses are also interconnected so that the individual source and gate regions operate in parallel. Thus, the device can, in effect, operate as a single MOS transistor.
2. Description of the Prior Art
The source electrode layer in prior art devices typically covers most of the main active area of the transistor device in a continuous layer. This results in a significant parasitic gate-to-source capacitance, which increases the turn-on and turn-off times as well as the current drive needed to switch the device. In addition, the insulating layer between the gate electrode and the source metal layer must provide a high degree of isolation over the large area of the source electrode layer. Imperfections such as pinholes or photomasking defects occurring during contact opening in the isolation layer can lead to eventual gate to source shorts. That is, during the metallization process, a metal bridge can be formed between the source electrode layer and the underlying gate electrode layer through an imperfection in the insulating layer, shorting the source and gate electrode layers.
Another disadvantage associated with prior art power MOSFET devices relates to the "on resistance" (R.sub.on) of the devices. The on resistance of a power MOSFET device is determined in part by the width of the individual gate electrode busses between the source regions. Generally, the higher the on resistance of a MOSFET device, the greater its power dissipation.
The source regions of the power transistors are generally formed in relatively narrow parallel lines with each line often referred to as a source bus. Each source bus has a plurality of expanded areas for accommodating the contact pads of the source electrode layer. The expanded areas of previous devices often have shapes such as octagons and hexagons. Since each gate bus follows the outline of adjacent source busses, the expanded areas of the source busses operate to reduce the effective width of the gate busses. Also, the expanded areas of previous devices consume a large amount of space, which reduces the available packing density of the source busses.
In order to minimize the narrowing of the effective width of each gate bus, previous devices have been constructed so that the expanded areas adjacent source busses are interleaved. The interleaved structure complicates the generation of the masks used to construct the device and does not readily lend itself to a repetitious (step and repeat) computer-controlled generation procedure.